# A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

> Research article (Analog Integrated Circuits and Signal Processing, 2020) · cited 10× · AI/ML

**Wikidata**: [openalex:W3004594587](https://www.wikidata.org/wiki/openalex:W3004594587)  
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