# A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS

> Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 17× · AI/ML

**Wikidata**: [openalex:W2793132439](https://www.wikidata.org/wiki/openalex:W2793132439)  
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