# A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

> Research article (IEEE Transactions on Circuits & Systems II Express Briefs, 2015) · cited 29× · AI/ML

**Wikidata**: [openalex:W2277822878](https://www.wikidata.org/wiki/openalex:W2277822878)  
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