# A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

> Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 15× · AI/ML

**Wikidata**: [openalex:W2789665175](https://www.wikidata.org/wiki/openalex:W2789665175)  
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