# A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC

> Research article (2017 Symposium on VLSI Circuits, 2017) · cited 50× · AI/ML

**Wikidata**: [openalex:W2743325598](https://www.wikidata.org/wiki/openalex:W2743325598)  
**Source**: https://4ort.xyz/entity/a-calibration-free-2-3-mw-73-2-db-sndr-15b-100-ms-s-four-stage-fully-differential-ring-amplifier-based-sar-assisted-pipe