# A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

> Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 242× · AI/ML

**Wikidata**: [openalex:W2790511620](https://www.wikidata.org/wiki/openalex:W2790511620)  
**Source**: https://4ort.xyz/entity/a-65nm-4kb-algorithm-dependent-computing-in-memory-sram-unit-macro-with-2-3ns-and-55-8tops-w-fully-parallel-product-sum-