# A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

> Research article (AEU - International Journal of Electronics and Communications, 2017) · cited 34× · AI/ML

**Wikidata**: [openalex:W2776212486](https://www.wikidata.org/wiki/openalex:W2776212486)  
**Source**: https://4ort.xyz/entity/a-5-76-0-ghz-cmos-pll-with-low-phase-noise-and-68-dbc-reference-spur