# A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS

> Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019) · cited 23× · AI/ML

**Wikidata**: [openalex:W2944515859](https://www.wikidata.org/wiki/openalex:W2944515859)  
**Source**: https://4ort.xyz/entity/a-43-6-db-sndr-1-gs-s-3-2-mw-sar-adc-with-background-calibrated-fine-and-coarse-comparators-in-28-nm-cmos