# A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays

> Research article (2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022) · cited 48× · AI/ML

**Wikidata**: [openalex:W4286571956](https://www.wikidata.org/wiki/openalex:W4286571956)  
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