# A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

> Research article (IEEE Journal of Solid-State Circuits, 2019) · cited 48× · AI/ML

**Wikidata**: [openalex:W2972420192](https://www.wikidata.org/wiki/openalex:W2972420192)  
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