# A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

> Research article (IEEE Journal of Solid-State Circuits, 2021) · cited 19× · AI/ML

**Wikidata**: [openalex:W3202672454](https://www.wikidata.org/wiki/openalex:W3202672454)  
**Source**: https://4ort.xyz/entity/a-24-gb-s-pin-8-gb-gddr6-with-a-half-rate-daisy-chain-based-clocking-architecture-and-i-o-circuitry-for-low-noise-operat