# A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

> Research article (2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022) · cited 23× · AI/ML

**Wikidata**: [openalex:W4220841253](https://www.wikidata.org/wiki/openalex:W4220841253)  
**Source**: https://4ort.xyz/entity/a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra