# A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications

> Research article (2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016) · cited 13× · AI/ML

**Wikidata**: [openalex:W2525807338](https://www.wikidata.org/wiki/openalex:W2525807338)  
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