# A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI

> Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021) · cited 18× · AI/ML

**Wikidata**: [openalex:W3194836568](https://www.wikidata.org/wiki/openalex:W3194836568)  
**Source**: https://4ort.xyz/entity/a-16-kb-9t-ultralow-voltage-sram-with-column-based-split-cell-vss-data-aware-write-assist-and-enhanced-read-sensing-marg