# A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology

> Research article (ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017) · cited 27× · AI/ML

**Wikidata**: [openalex:W2769943552](https://www.wikidata.org/wiki/openalex:W2769943552)  
**Source**: https://4ort.xyz/entity/a-14-bit-1-ps-resolution-two-step-ring-and-2d-vernier-tdc-in-130nm-cmos-technology