# A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration

> Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 10× · AI/ML

**Wikidata**: [openalex:W4360605520](https://www.wikidata.org/wiki/openalex:W4360605520)  
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