# A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

> Research article (2018 IEEE Custom Integrated Circuits Conference (CICC), 2018) · cited 21× · AI/ML

**Wikidata**: [openalex:W2801792298](https://www.wikidata.org/wiki/openalex:W2801792298)  
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