# A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

> Research article (IEEE Journal of Solid-State Circuits, 2018) · cited 214× · AI/ML

**Wikidata**: [openalex:W2799859329](https://www.wikidata.org/wiki/openalex:W2799859329)  
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