# A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS

> Research article (IEEE Journal of Solid-State Circuits, 2015) · cited 37× · AI/ML

**Wikidata**: [openalex:W1996194487](https://www.wikidata.org/wiki/openalex:W1996194487)  
**Source**: https://4ort.xyz/entity/a-0-41-pj-bit-10-gb-s-hybrid-2-iir-and-1-discrete-time-dfe-tap-in-28-nm-lp-cmos