# A 0.0056mm<sup>2</sup> all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and −249dB FOM

> Research article (2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018) · cited 19× · AI/ML

**Wikidata**: [openalex:W2790292185](https://www.wikidata.org/wiki/openalex:W2790292185)  
**Source**: https://4ort.xyz/entity/a-0-0056mm-sup-2-sup-all-digital-mdll-using-edge-re-extraction-dual-ring-vcos-and-a-0-3mw-block-sharing-frequency-tracki