# 9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS

> Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 97× · AI/ML

**Wikidata**: [openalex:W2288286056](https://www.wikidata.org/wiki/openalex:W2288286056)  
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