# 8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

> Research article (2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017) · cited 18× · AI/ML

**Wikidata**: [openalex:W2593145514](https://www.wikidata.org/wiki/openalex:W2593145514)  
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