# 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

> Research article (2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020) · cited 138× · AI/ML

**Wikidata**: [openalex:W3016048022](https://www.wikidata.org/wiki/openalex:W3016048022)  
**Source**: https://4ort.xyz/entity/33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights