# 27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS

> Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 53× · AI/ML

**Wikidata**: [openalex:W2289098659](https://www.wikidata.org/wiki/openalex:W2289098659)  
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