# 2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL

> Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 16× · AI/ML

**Wikidata**: [openalex:W2292416786](https://www.wikidata.org/wiki/openalex:W2292416786)  
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