# 19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation

> Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 27× · AI/ML

**Wikidata**: [openalex:W2288499521](https://www.wikidata.org/wiki/openalex:W2288499521)  
**Source**: https://4ort.xyz/entity/19-5-a-3-2ghz-digital-phase-locked-loop-with-background-supply-noise-cancellation