# 17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

> Research article (2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020) · cited 50× · AI/ML

**Wikidata**: [openalex:W3015425606](https://www.wikidata.org/wiki/openalex:W3015425606)  
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