# 17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input

> Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 13× · AI/ML

**Wikidata**: [openalex:W4360605767](https://www.wikidata.org/wiki/openalex:W4360605767)  
**Source**: https://4ort.xyz/entity/17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh