# 17.1 A −240dB-FoM<sub>jitter</sub> and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction

> Research article (2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020) · cited 15× · AI/ML

**Wikidata**: [openalex:W3015561111](https://www.wikidata.org/wiki/openalex:W3015561111)  
**Source**: https://4ort.xyz/entity/17-1-a-240db-fom-sub-jitter-sub-and-115dbc-hz-pn-100khz-7-7ghz-ring-dco-based-digital-pll-using-p-i-gain-co-optimization