# 16.6 A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and-70dBc Fractional Spurs

> Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 20× · AI/ML

**Wikidata**: [openalex:W2920923622](https://www.wikidata.org/wiki/openalex:W2920923622)  
**Source**: https://4ort.xyz/entity/16-6-a-calibration-free-triple-loop-bang-bang-pll-achieving-131fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-70dbc-fractional-sp
