# 16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

> Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 60× · AI/ML

**Wikidata**: [openalex:W2921046765](https://www.wikidata.org/wiki/openalex:W2921046765)  
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