# 14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

> Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 38× · AI/ML

**Wikidata**: [openalex:W2922193163](https://www.wikidata.org/wiki/openalex:W2922193163)  
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