14.4 A 5GHz &#x2212;95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS
Research article (2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015) · cited 11× · AI/ML