# 14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

> Research article (2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015) · cited 11× · AI/ML

**Wikidata**: [openalex:W2008181086](https://www.wikidata.org/wiki/openalex:W2008181086)  
**Source**: https://4ort.xyz/entity/14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con