# 11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

> Research article (2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024) · cited 13× · AI/ML

**Wikidata**: [openalex:W4392746399](https://www.wikidata.org/wiki/openalex:W4392746399)  
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