# 10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving −73dBc fractional spur and −110dBc Reference Spur in 65nm CMOS

> Research article (2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016) · cited 10× · AI/ML

**Wikidata**: [openalex:W2292016009](https://www.wikidata.org/wiki/openalex:W2292016009)  
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