{"schema_version":"4ort.packet/1","entity":{"entity_id":"hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition","kg_uuid":"9c447205-2ae5-4471-8061-528676d849f7","wikidata_id":"openalex:W2750971660","name":"Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition","description":"Research article (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017) · cited 85× · AI/ML","type":"CreativeWork","url":"https://4ort.xyz/entity/hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition"},"status":"complete","as_of":{"copy_written_at":"2026-10-17T03:10:53Z","last_source_edit_seen":null,"stale_possible":false},"facts":[{"field":"P31","label":"instance of","value":"scholarly article","value_id":"Q13442814","value_raw":"Q13442814","rank":"normal","current":null,"qualifiers":[],"layer":"source","citation":{"source":"openalex","source_name":"OpenAlex","source_record":"https://openalex.org/W2750971660","source_edition":null,"edition_basis":"unknown","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"references":[]},"trust":{"band":"high","basis":"dataset-record/1","calibrated":false}},{"field":"P577","label":"publication date","value":"2017-08-31","value_id":null,"value_raw":"+2017-08-31T00:00:00Z","rank":"normal","current":null,"qualifiers":[],"layer":"source","citation":{"source":"openalex","source_name":"OpenAlex","source_record":"https://openalex.org/W2750971660","source_edition":"20260923","edition_basis":"lake_edition","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"references":[]},"trust":{"band":"high","basis":"dataset-record/1","calibrated":false}},{"field":"P356","label":"DOI","value":"10.1109/TCAD.2017.2748024","value_id":null,"value_raw":"10.1109/TCAD.2017.2748024","rank":"normal","current":null,"qualifiers":[],"layer":"source","citation":{"source":"openalex","source_name":"OpenAlex","source_record":"https://openalex.org/W2750971660","source_edition":"20260923","edition_basis":"lake_edition","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"references":[]},"trust":{"band":"high","basis":"dataset-record/1","calibrated":false}},{"field":"P1433","label":"published in","value":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","value_id":"Q5970503","value_raw":"Q5970503","rank":"normal","current":null,"qualifiers":[],"layer":"source","citation":{"source":"openalex","source_name":"OpenAlex","source_record":"https://openalex.org/W2750971660","source_edition":"20260923","edition_basis":"lake_edition","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"references":[]},"trust":{"band":"high","basis":"dataset-record/1","calibrated":false}},{"field":"P1476","label":"title","value":"Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition","value_id":null,"value_raw":{"lang":"en","text":"Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition"},"rank":"normal","current":null,"qualifiers":[],"layer":"source","citation":{"source":"openalex","source_name":"OpenAlex","source_record":"https://openalex.org/W2750971660","source_edition":"20260923","edition_basis":"lake_edition","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"references":[]},"trust":{"band":"high","basis":"dataset-record/1","calibrated":false}}],"unknowns":[],"omitted":{"facts":0,"reason":null},"licences":[{"source":"openalex","source_name":"OpenAlex","licence":"CC0 1.0 Universal","licence_url":"https://creativecommons.org/publicdomain/zero/1.0/","attribution":null,"fields":["P31","P577","P356","P1433","P1476"]}],"routes":{"entity_page":"https://4ort.xyz/entity/hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition","packet_api":"https://4ort.xyz/api/v1/entities/hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition/packet","facts_jsonld":"https://4ort.xyz/entity/hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition/facts.json","changes_api":"https://4ort.xyz/api/v1/knowledge/get_entity_changes?entity=hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition","attention_api":"https://4ort.xyz/api/v1/knowledge/get_attention?entity=hierarchical-temporal-memory-features-with-memristor-logic-circuits-for-pattern-recognition","wikidata":null,"official_website":null},"trust_rules":{"dataset-record/1":"The fact is the cited dataset's own published record (band high). Reference support, not a probability."},"notes":[]}